As lithographic feature size is reduced in successive generations of dynamic random access memory components (DRAM), the capacitance of individual storage cells is reduced. The leakage current of the access transistor element increases in each successive generation because of the reduction in gate threshold voltage. The retention time of a dynamic storage cell is proportional to the storage capacitance divided by leakage current. Consequently, the trend is for the average retention time to decrease at each process generation.
Each storage cell must be refreshed periodically by sensing a row and rewriting it—the parameter for the interval between successive sensing operations is called the refresh time, or tREF. The tREF interval must be less than the retention time interval of every storage cell on each DRAM component.
A DRAM component is tested for the tREF parameter at the time of manufacture. This testing is performed at worst case temperature and supply voltage. If the retention time of a storage cell degrades after it has been manufactured, the DRAM (and a module or board into which it is soldered) will become unusable. Among other things, a method of detecting storage cells with degraded retention times and correcting for them is disclosed in various embodiments in this description.
Embodiments herein monitor the retention time of a memory device by checking each access for errors. In this manner, all rows may be effectively tested in parallel. The testing described herein also has little-to-no impact on DRAM performance since live data in the rows does not need to be moved by the retention monitoring process. When the retention monitoring process discovers a storage cell with a degraded retention time, it will update the repair map for a repair method.